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    參數(shù)資料
    型號: MPC8343ECVRAGD
    廠商: Freescale Semiconductor
    文件頁數(shù): 57/80頁
    文件大小: 0K
    描述: IC MPU PWRQUICC II PRO 620-PBGA
    標(biāo)準(zhǔn)包裝: 36
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 400MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 620-BBGA 裸露焊盤
    供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
    包裝: 托盤
    MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
    60
    Freescale Semiconductor
    Clocking
    19 Clocking
    Figure 37 shows the internal distribution of the clocks.
    Figure 37. MPC8343EA Clock Subsystem
    The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
    is configured in PCI host or PCI agent mode. When the MPC8343EA is configured as a PCI host device,
    CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
    ÷2) and the multiplexors for
    PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
    CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
    whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
    PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
    synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
    with equal delay to all PCI agent devices in the system, to allow the MPC8343EA to function. When the
    device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
    should be tied to GND.
    Core PLL
    System PLL
    DDR
    LBIU
    LSYNC_IN
    LSYNC_OUT
    LCLK[0:2]
    MCK[0:3]
    core_clk
    e300 Core
    csb_clk to Rest
    CLKIN
    csb_clk
    MPC8343EA
    4
    DDR
    Memory
    Local Bus
    PCI_CLK_OUT[0:4]
    PCI_SYNC_OUT
    PCI_CLK/
    Clock
    Unit
    of the Device
    ddr_clk
    lbiu_clk
    CFG_CLKIN_DIV
    PCI Clock
    PCI_SYNC_IN
    Device
    Memory
    Device
    /n
    To Local Bus
    Memory
    Controller
    To DDR
    Memory
    Controller
    DLL
    Clock
    Div
    /2
    Divider
    5
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    MPC8343ECVRAGDB 功能描述:微處理器 - MPU 8347 PBGA NO-PB W/ ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8343ECZQADDB 功能描述:微處理器 - MPU 8347 PBGA ENCRYP W/ PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8343ECZQAGDB 功能描述:微處理器 - MPU 8347 PBGA ENCRYP W/ PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8343EVRADD 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA(29x29) 包裝:托盤
    MPC8343EVRADDB 功能描述:微處理器 - MPU 8347 PBGA NO-PB W/ ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324