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參數(shù)資料
| 型號： | MPC8323CZQAFDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC II 516-PBGA |
| 產品培訓模塊： | MPC8323E PowerQUICC II Pro Processor |
| 標準包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應商設備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
| 配用： | MPC8323E-RDB-ND - BOARD REFERENCE DESIGN |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
12
Freescale Semiconductor
RESET Initialization
Table 10 provides the PLL lock times.
5.1
Reset Signals DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 9.
HRESET/SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI host mode
4—
tCLKIN
2
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to negation of
HRESET
0—
ns
—
Time for the MPC8323E to turn off POR configuration signals with respect
to the assertion of HRESET
—4
ns
3
Time for the MPC8323E to turn on POR configuration signals with respect
to the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the
primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See
the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs—
Table 11. Reset Signals DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Input high voltage
VIH
—2.0
OVDD +0.3
V
1
Input low voltage
VIL
—
–0.3
0.8
V
—
Table 9. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Notes
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相關代理商/技術參數(shù) |
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|---|---|
| MPC8323CZQAFDCA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323E_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323ECVRADDC | 功能描述:微處理器 - MPU 8323 NOPB PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8323ECVRADDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 266MHZ E300, QE, - Trays |
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