參數(shù)資料
型號： MPC8314EVRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 88/101頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 620-PBGA
標準包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
87
Clocking
This table provides the operating frequencies for the TEPBGA II under recommended operating
conditions (see Table 2).
23.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 69 shows the multiplication factor
encodings for the system PLL.
NOTE
If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL
VCO frequency = (CSB frequency)
(System PLL VCO Divider).
If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO
frequency = 2
(CSB frequency) (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 450–750 MHz.
Table 67. Configurable Clock Units
Unit
Default Frequency
Options
eTSEC1
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
eTSEC2
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Security Core, I2C, SAP, TPR
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
USB DR
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
PCI Express
csb_clk
Off, csb_clk
Serial ATA
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Table 68. Operating Frequencies for TEPBGA II
Characteristic1
Max Operating Frequency
Unit
e300 core frequency (core_clk)
400
MHz
Coherent system bus frequency (csb_clk)
133
MHz
DDR1/2 memory bus frequency (MCK)2
133
MHz
Local bus frequency (LCLKn)3
66
MHz
PCI input frequency (SYS_CLK_IN or PCI_CLK)
24-66
MHz
Note:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCK, LCLK[0:1], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1x or 2x the
csb_clk frequency (depending on RCWL[LBCM]).
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