參數(shù)資料
型號: MPC8313EZQADDB
廠商: Freescale Semiconductor
文件頁數(shù): 60/99頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 516-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 267MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
63
This figure shows the SPI timing in slave mode (external clock).
Figure 54. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in master mode (internal clock).
Figure 55. SPI AC Timing in Master Mode (Internal Clock) Diagram
19 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in
a thermally enhanced plastic ball grid array (TEPBGAII), see Section 19.1, “Package Parameters for the
information on the TEPBGAII.
19.1
Package Parameters for the MPC8313E TEPBGAII
The package parameters are as provided in the following list. The package type is 27 mm
27 mm,
516 TEPBGAII.
Package outline
27 mm
Interconnects
516
Pitch
1.00 mm
Module height (typical)
2.25 mm
Solder Balls
96.5 Sn/3.5 Ag(VR package) ,
62 Sn/36 Pb/2 Ag (ZQ package) Ball diameter (typical)
0.6 mm
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (Output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
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