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參數(shù)資料
| 型號： | MPC8313E-RDBB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 76/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD CPU 8313E VER 2.1 |
| 標準包裝： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 類型： | MPU |
| 適用于相關產(chǎn)品： | MPC8313E |
| 所含物品： | 板 |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
78
Freescale Semiconductor
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. When the device is
configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI
clock divider (
2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The
CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or SYS_CLK_IN/2 is driven out
on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether the PCI_SYNC_OUT
is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the SYS_CLK_IN signal should be tied to VSS.
As shown in Figure 57, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbc_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the SYS_CLK_IN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8313E PowerQUICC II Pro Integrated Processor Family
Reference Manual, for more information on the clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbc_clk frequency is determined by the following equation:
lbc_clk = csb_clk × (1 + RCWL[LBCM])
Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the a LBC clock divider
to create the external local bus clock outputs (LCLK[0:1]). The LBC clock divider ratio is controlled by
LCRR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 63 specifies which units have a configurable clock
frequency.
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| STD12W-T | WIRE & CABLE MARKERS |
| STD12W-X | WIRE & CABLE MARKERS |
| STD12W-F | WIRE & CABLE MARKERS |
| STD12W-G | WIRE & CABLE MARKERS |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8313E-RDBB | 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MPC8313E-RDBC | 功能描述:開發(fā)板和工具包 - 其他處理器 8313E CPU board Ver 2.2 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8313EVRADD | 制造商:Freescale Semiconductor 功能描述:MPC83XX RISC 32-BIT 90NM 333MHZ 1V/1.8V/2.5V/3.3V 516-PIN TE - Trays |
| MPC8313EVRADDB | 功能描述:微處理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8313EVRADDC | 功能描述:微處理器 - MPU 8313 REV2.2 W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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