• <li id="qfmmm"><meter id="qfmmm"><sup id="qfmmm"></sup></meter></li>
    • <table id="qfmmm"><tr id="qfmmm"></tr></table>
    • 參數(shù)資料
      型號: MPC8313CZQADDB
      廠商: Freescale Semiconductor
      文件頁數(shù): 98/99頁
      文件大?。?/td> 0K
      描述: MPU POWERQUICC II PRO 516-PBGA
      標準包裝: 40
      系列: MPC83xx
      處理器類型: 32-位 MPC83xx PowerQUICC II Pro
      速度: 267MHz
      電壓: 0.95 V ~ 1.05 V
      安裝類型: 表面貼裝
      封裝/外殼: 516-BBGA 裸露焊盤
      供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
      包裝: 托盤
      MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
      98
      Freescale Semiconductor
      1
      3/2008
      In Table 63, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1
      In Table 63, added LSRCID2 as muxed with USBDR_PCTL0
      In Table 63, added LSRCID1 as muxed with USBDR_PWRFAULT
      In Table 63, added LSRCID0 as muxed with USBDR_DRIVE_VBUS
      In Table 63, moved T1, U2,& V2 from VDD to XCOREVDD.
      In Table 63, moved P2, R2, & T3 from VSS to XCOREVSS.
      In Table 63, moved P5, & U4 from VDD to XPADVDD.
      In Table 63, moved P3, & V4 from VSS to XPADVSS.
      In Table 63, removed “Double with pad” for AVDD1 and AVDD2 and moved AVDD1 and AVDD2 to Power
      and Ground Supplies section
      In Table 63, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and
      SD_IMP_CAL_RX (200 ohms to GND).
      In Table 63, updated muxing in pinout to show new options for selecting IEEE 1588 functionality. Added
      footnote 8
      In Table 63, updated muxing in pinout to show new LBC ECC boot enable control muxed with
      eTSEC1_MDC
      Added pin type information for power supplies.
      Removed N1 and N3 from Vss section of Table 63. Added Therm0 and Therm1 (N1 and N3,
      respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies linearly
      with temperature. Useful for determining the junction temperature.”
      In Table 65 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz
      In Table 65 corrected maximum frequency of PCI from “24–66” to 66 MHz
      Added “which is determined by RCWLR[COREPLL],” to the note in Section 20.2, “Core PLL
      Configuration” about the VCO divider.
      Added “(VCOD)” next to VCO divider column in Table 68. Added footnote stating that core_clk
      frequency must not exceed its maximum, so 2.5:1 and 3:1 core_clk:csb_clk ratios are invalid for certain
      csb_clk values.
      In Table 69, notes were confusing. Added note 3 for VCO column, note 4 for CSB (csb_clk) column,
      note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum eTSEC40.
      In Table 69, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev. 2
      silicon.
      Replaced Table 71 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.
      Removed last row of Table 19.
      Removed 200 MHz rows from Table 21 and Table 5.
      Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,
      Table 47, Table 54, Table 59, and Table 61.
      Added Figure 4 showing the DDR input timing diagram.
      In Table 19, removed “MDM” from the “MDQS-MDQ/MECC/MDM” text under the Parameter
      column for the tCISKEW parameter. MDM is an output signal and should be removed from
      the input AC timing spec table (tCISKEW).
      Added “and power” to rows 2 and 3 in Table 10
      Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power
      Sequencing,” and Figure 3.
      In Figure 35, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”
      In Table 42, clarified that AC specs are for ULPI only.
      0
      6/2007
      Initial release.
      Table 73. Document Revision History (continued)
      Rev.
      Number
      Date
      Substantive Change(s)
      相關(guān)PDF資料
      PDF描述
      MPC8315ECVRADDA MPU POWERQUICC II PRO 620-PBGA
      AMM43DRMT-S288 CONN EDGECARD 86POS .156 EXTEND
      MPC8314EVRAGDA MPU POWERQUICC II PRO 620-PBGA
      AMC60DRTN-S734 CONN EDGECARD 120PS DIP .100 SLD
      MPC8323CVRAFDC IC MPU PWRQUICC II 516-PBGA
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      MPC8313CZQADDC 功能描述:微處理器 - MPU 8313 REV2.2 PB NO EN EXT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
      MPC8313CZQAFD 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
      MPC8313CZQAFDA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
      MPC8313CZQAFDB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
      MPC8313CZQAFF 功能描述:微處理器 - MPU 8313 PB PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324