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    參數(shù)資料
    

    


    


    
型號(hào)：
MPC8266CZU

    

    
廠商：
Motorola, Inc.

    

    
英文描述：
MPC826xA (HiP4) Family Hardware Specifications

    

    
中文描述：
MPC826xA（HiP4）家庭硬件規(guī)格

    

    
文件頁(yè)數(shù)：
23/48頁(yè)

    

    
文件大小：
315K

    

    
代理商：
MPC8266CZU


    

    

    

	
    
    
    

    
    
	
    MOTOROLA
    MPC826xA (HiP4) Family Hardware Specifications
    23
    Clock Configuration Modes
    1.3.2
    PCI Mode 
    The MPC8265 and the MPC8266 have three clocking modes: local, PCI host, and PCI agent. The clocking
    mode is set according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in
    Table 14.
    In addition, note the following:
    NOTE: PCI_MODCK
    In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
    MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
    NOTE: Tval (Output Hold)
    The minimum Tval = 2 when PCI_MODCK = 1, and the minimum
    Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock
    configurations that fit this condition to achieve PCI-compliant AC timing.
    NOTE
    Clock configurations change only after POR is asserted.
    0111_111
    66 MHz
    3.5
    233 MHz
    2
    133 MHz
    1000_000
    66 MHz
    3.5
    233 MHz
    2.5
    166 MHz
    1000_001
    66 MHz
    3.5
    233 MHz
    3
    200 MHz
    1000_010
    66 MHz
    3.5
    233 MHz
    3.5
    233 MHz
    1000_011
    66 MHz
    3.5
    233 MHz
    4
    266 MHz
    1000_100
    66 MHz
    3.5
    233 MHz
    4.5
    300 MHz
    1  
    Because of speed dependencies, not all of the possible configurations in Table 13 are applicable.
    2  
    The user should choose the input clock frequency and the multiplication factors such that the frequency of the 
    CPU is equal to or greater than150 MHz and the CPM ranges between 66–233 MHz.
    3  
    Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that 
    the resulting configuration does not exceed the frequency rating of the user’s part. 
    Table 14. MPC8265 and MPC8266 Clocking Modes
    Pins
    Clocking Mode
    PCI Clock 
    Frequency Range
    (MHZ)
    PCI_MODE PCI_CFG[0] PCI_MODCK 
    1
    —
    —
    Local bus
    —
    0
    0
    0
    PCI host 
    50–66
    0
    0
    1
    25–50
    0
    1
    0
    PCI agent 
    50–66
    0
    1
    1
    25–50
    Table 13. Clock Configuration Modes
    1
     (Continued)
    MODCK_H–MODCK[1–3]
    Input Clock 
    Frequency
    2,3
    CPM Multiplication 
    Factor
    2
    CPM
    Frequency
    2
    Core Multiplication 
    Factor
    2
    Core
    Frequency
    2
    
    
    
    
    
    


    


    

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