參數(shù)資料
型號(hào)： MPC8264CZU
廠商： Motorola, Inc.
英文描述： MPC826xA (HiP4) Family Hardware Specifications
中文描述： MPC826xA（HiP4）家庭硬件規(guī)格
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 315K
代理商： MPC8264CZU
26
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
Clock Configuration Modes
1001_100
66 MHz
3.5
233 MHz
4.5
300 MHz
4/8
58/29 MHz
1010_000
100 MHz
2
200 MHz
2
200 MHz
3/6
66/33 MHz
1010_001
100 MHz
2
200 MHz
2.5
250 MHz
3/6
66/33 MHz
1010_010
100 MHz
2
200 MHz
3
300 MHz
3/6
66/33 MHz
1010_011
100 MHz
2
200 MHz
3.5
350 MHz
3/6
66/33 MHz
1010_100
100 MHz
2
200 MHz
4
400 MHz
3/6
66/33 MHz
1011_000
100 MHz
2.5
250 MHz
2
200 MHz
4/8
62/31 MHz
1011_001
100 MHz
2.5
250 MHz
2.5
250 MHz
4/8
62/31MHz
1011_010
100 MHz
2.5
250 MHz
3
300 MHz
4/8
62/31 MHz
1011_011
100 MHz
2.5
250 MHz
3.5
350 MHz
4/8
62/31 MHz
1011_100
100 MHz
2.5
250 MHz
4
400 MHz
4/8
62/31 MHz
1
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
2
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.). Refer to Table 14.
3
In this mode, PCI_MODCK must be “0”.
Table 16. Clock Configuration Modes in PCI Host Mode (Continued)
MODCK_H –
MODCK[1–3]
Input Clock
Frequency
1
(Bus)
CPM
Multiplication
Factor
CPM
Frequency
Core
Multiplication
Factor
Core
Frequency
PCI Division
Factor
2
PCI
Frequency
2
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