
Communication Processor Module
16-148
MPC823 USER’S MANUAL
MOTOROLA
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
2. SIMODE = 0x0000c000. SCC2 is connected to the time-slot assigner. SCC2 supports
the grant mechanism since it is on the D channel.
3. SICR = 0x000040C0. SCC2 is connected to the time-slot assigner.
4. PAODR bit 9 = 1. Configure L1TXDa to be an open-drain output.
5. PAPAR bits 9, 8, and 7= 1. Configure L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR bits 9 and 8 = 1.PADIR bit 7 = 0. Configure L1TXDa, L1RXDa, and L1RCLKa.
7. PCPAR bit 4 = 1. Configure L1RSYNCa.
8. SIGMR = 0x04.Enable TDMa (one static TDM).
9. SICMR is not used.
10. SISTR and SIRP do not need to be read, but can be used for debugging information
once the channels are enabled.
11. Enable SCC2 for HDLC operation (to handle the LAPD protocol of the D channel). Set
SMC1 for SCIT operation. Set SMC2 for transparent operation.
16.7.8 Nonmultiplexed Serial Interface Configuration
The serial interface supports a nonmultiplexed serial interface (NMSI) mode for the serial
communication controller and serial management controllers. The decision of whether to
connect SCC2 to the NMSI is made in the SICR and the decision of whether to connect a
serial management controller to the NMSI is made in the SIMODE register. The serial
communication controller or serial management controllers can be connected to the NMSI,
regardless of the other channels connected to a TDM channel. You should keep in mind,
however, that NMSI pins can be multiplexed with other functions at the parallel I/O lines.
Therefore, if a combination of the TDMA and NMSI channels is used, you should consult the
controller or serial management controller to connect and where to connect them.
The clocks that are provided to the universal serial bus, serial communication controller, and
serial management controllers are derived from six sources—four internal baud rate
generators and four external CLK pins. There are two main advantages to this
bank-of-clocks approach. First, a universal serial bus, serial communication controller, or
serial management controller is not forced to choose its clock from a predefined pin or baud
rate generator, which adds flexibility to the pinout mapping strategy. Second, if a group of
SMC receivers and transmitters need the same clock rate they can share the same pin,
which leaves other pins available for other functions and minimizes the potential skew
between multiple clock sources.
Note: If SCIT mode is not used, delete the last three entries of the serial interface RAM
and set the LST bit in the new last entry.