參數(shù)資料
型號： MPC755CVT400LE
廠商： Freescale Semiconductor
文件頁數(shù)： 45/56頁
文件大?。?/td> 0K
描述： MCU HIP4DP 400MHZ 360-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 400MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 360-BBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
5
General Parameters
— Selectable interface voltages of 2.5 and 3.3 V
— Parity checking on both L2 address and data
Memory management unit
— 128-entry, two-way set-associative instruction TLB
— 128-entry, two-way set-associative data TLB
— Hardware reload for TLBs
— Hardware or optional software tablewalk support
— Eight instruction BATs and eight data BATs
— Eight SPRGs, for assistance with software tablewalks
— Virtual memory support for up to 4 exabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
Bus interface
— Compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus, 32-bit mode selectable
— Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x
supported
— Selectable interface voltages of 2.5 and 3.3 V
— Parity checking on both address and data buses
Power management
— Low-power design with thermal requirements very similar to MPC740/MPC750
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
Integrated thermal management assist unit
— On-chip thermal sensor and control logic
— Thermal management interrupt for software regulation of junction temperature
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
3
General Parameters
The following list provides a summary of the general parameters of the MPC755:
Technology
0.22 m CMOS, six-layer metal
Die size
6.61 mm
× 7.73 mm (51 mm2)
Transistor count
6.75 million
Logic design
Fully-static
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