參數(shù)資料
型號： MPC745BVT350LE
廠商： Freescale Semiconductor
文件頁數(shù)： 54/56頁
文件大小： 0K
描述： IC MPU PPC 350MHZ 255-FCPBGA
標準包裝： 60
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 350MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 255-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 255-FCPBGA（21x21）
包裝： 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
7
Electrical and Thermal Characteristics
Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755.
Figure 2. Overshoot/Undershoot Voltage
The MPC755 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC755 core voltage must always be provided at nominal 2.0 V (see
Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and
L2VSEL during operation. These signals must remain stable during part operation and cannot change. The
output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power
pins.
Table 2 describes the input threshold voltage setting.
Table 2. Input Threshold Voltage Setting
Part
Revision
BVSEL Signal
Processor Bus
Interface Voltage
L2VSEL Signal
L2 Bus
Interface Voltage
E
0
Not Available
0
Not Available
1
2.5 V/3.3 V
1
2.5 V/3.3 V
Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.
Note: The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information,
VIH
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
(L2)OVDD + 20%
VIL
(L2)OVDD
(L2)OVDD + 5%
of tSYSCLK
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