參數(shù)資料
型號(hào)： MPC7410THX500LE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 12/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 500MHZ 360-CBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 500MHz
電壓： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 360-BBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
2
Freescale Semiconductor
Features
The MPC7410 is implemented in a next generation process technology for core frequency improvement.
The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision
operations involving multiplication.
The completion queue has been extended to eight slots.
There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the
branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute,
complete/writeback).
Some comments on the MPC7410 with respect to the MPC7400:
The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface.
The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2
address pin (L2ASPARE on the MPC7400) in order to support additional address range.
The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.
Figure 1 shows a block diagram of the MPC7410.
2Features
This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major features of
the MPC7410 are as follows:
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay
slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1,
fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)
— Serialization control (predispatch, postdispatch, execution serialization)
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