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參數(shù)資料
| 型號(hào)： | MPC603RZT200LC |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 200MHZ PPC 255-PBGA |
| 產(chǎn)品變化通告： | NPD Devices Discontinuation 24/Aug/2012 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC6xx |
| 處理器類型： | 32-位 MPC603e PowerPC |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BBGA |
| 供應(yīng)商設(shè)備封裝： | 255-PBGA（23x23） |
| 包裝： | 托盤 |
2
PID7v-603e Specification Variances
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
The known errata as of the date of this document are summarized below.
Electrical and Thermal Characteristics
This section provides any changes to the AC and DC electrical specications and thermal characteristics for the PID6-603e parts
described herein.
DC Electrical Characteristics
This section describes the changed thermal operating conditions for the PID7t-603e part numbers described herein.
#
Problem
Description
Impact
Solutions
1
Snoop copyback causes dcbi to
broadcast wrong address.
A snoop which causes a copy-
back and occurs in a one cycle
window near a dcbi causes the
dcbi to broadcast the address
of the snoop copyback.
Only systems using both soft-
ware and hardware coherency
simultaneously.
Use software semaphores
rather than rely on dcbi to
invalidate cache lines shared
across multiple processors.
2
Competition for reservation
with lwarx/stwcx may cause
live-lock
The problem occurs when two
processors are competing on
the bus for a reservation, and
the bus is operating with
address pipelining
System Hang
Insert a bus clocks worth of
no-ops before lwarx
3
Touch load causes incorrect
address to appear on memory
bus
A touch load (dcbt) preceded
by an instruction that generates
an exception causes a random
address to appear on the mem-
ory bus
Systems issuing instructions
which generate mmu excep-
tions one cycle before using a
touch load instruction
Disable touch loads with
NOOPTI bit in HID0.
4
Write-thru stores followed by
dcbz followed by a snoop, all
to the same cache line, may
cause incoherency.
The sequence of write-thru
stores followed by dcbz fol-
lowed by a snoop, all to the
same cache line, may cause
incoherency.
The write-thru store is com-
pleted after the dcbz.
Store zeroes rather than rely on
dcbz to zero cache lines in
areas of memory that are
marked as write-thru and can
be accessed via multiple logi-
cal addresses.
5
The broadcasting of dcbz
instructions may retry snoop
accesses indenately.
A sequence of broadcast bcbz
instructions may retry snoop
accesses indenately.
Snoop originator may timeout.
Disable broadcasting of dcbz
by marking the memory space
being addressed by the dcbz
instruction as not global in the
BAT or PTE.
. Recommended Operating Conditions
Characteristic
Symbol
Value
Unit
Notes
Junction temperature
TJ
-40 to 105
°C
Note: 1. Parts with TC sufx only.
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.
Freescale Semiconductor, Inc.
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