參數(shù)資料
型號(hào): MPC5646CCF0MLU1R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 120 MHz, MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-176
文件頁(yè)數(shù): 91/115頁(yè)
文件大?。?/td> 783K
代理商: MPC5646CCF0MLU1R
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Electrical Characteristics
MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
77
CS
CC
D ADC_0 input
sampling
capacitance
——
3
pF
CP1
CC
D ADC_0 input pin
capacitance 1
——
3
pF
CP2
CC
D ADC_0 input pin
capacitance 2
——
1
pF
CP3
CC
D ADC_0 input pin
capacitance 3
——
1
pF
RSW1
CC
D Internal resistance of
analog source
——
3
k
RSW2
CC
D Internal resistance of
analog source
2
k
RAD
CC
D Internal resistance of
analog source
——
2
k
IINJ
SR — Input current Injection Current
injection on
one ADC_0
input, different
from the
converted one
VDD =
3.3 V ± 10%
5—
5
mA
VDD =
5.0 V ± 10%
5
5
| INL |
CC
T Absolute value for
integral non-linearity
No overload
0.5
1.5
LSB
| DNL |
CC
T Absolute differential
non-linearity
No overload
0.5
1.0
LSB
| OFS |
CC
T Absolute offset error
0.5
LSB
| GNE |
CC
T Absolute gain error
——
0.6
LSB
TUEP
CC
P Total unadjusted
error7 for precise
channels, input only
pins
Without current injection
2
0.6
2
LSB
T
With current injection
3
TUEX
CC
T Total unadjusted
error(7) for extended
channel
Without current injection
3
1
3
LSB
T
With current injection
4
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 Analog and digital V
SS_HV must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4 During the sample time the input capacitance C
S can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
5 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
Table 42. ADC conversion characteristics (10-bit ADC_0) (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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