
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-1
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
The U-bus to IMB3 bus interface (UIMB) structure is used to connect the CPU internal unified bus (U-bus)
to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3. The
UIMB interface (see
Figure 12-1) consists of seven submodules that control bus interface timing, address
decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow
communication between U-bus and the IMB3. The seven submodules are:
U-bus interface
IMB3 interface
Address decoder
Data multiplexer
Interrupt synchronizer
Clock control
Scan control
12.1
Features
Provides complete interfacing between the U-bus and the IMB3:
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface address range
— Burst-inhibited accesses to the modules on IMB3
Support of 32-bit and 16-bit bus interface units (BIUs) for IMB3 modules
Half and full speed operation of IMB3 bus with respect to U-bus
Simple “slave only” U-bus interface implementation
— Transparent mode operation not supported
— Relinquish and retry not supported
Supports scan control for modules on the IMB3 and on the U-bus
NOTE
Modules on the IMB3 bus can only be reset by SRESET. Some modules
may have a module reset, as well.