參數資料
型號： MPC5607BMLL4R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 48 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, MS-026 BED, LQFP-100
文件頁數： 59/106頁
文件大?。?/td> 667K
代理商： MPC5607BMLL4R
MPC5607B Microcontroller Data Sheet, Rev. 5
Electrical characteristics
Freescale Semiconductor
56
4.10
Flash memory electrical characteristics
4.10.1
Program/erase characteristics
Table 24 shows the program and erase characteristics.
5 RUN current measured with typical application with accesses on both Flash and RAM.
6 Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and
LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and
running at max frequency, periodic SW/WDG timer reset enabled.
7 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance:
0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI:
instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1
OFF. ADC0 ON but no conversion except two analog watchdogs.
8 Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
9 Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched off.
10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
Table 24. Program and erase specifications
Symbol
C
Parameter
Conditions
Value
Unit
Min Typ1
change pending device characterization.
Initial
max2
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
Max3
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
Tdwprogram
CC C Double word (64 bits) program time4
4 Actual hardware programming times. This does not include software overhead.
Code Flash
—
18
50
500
s
Data Flash
22
T16Kpperase
16 KB block preprogram and erase time
Code Flash
—
200
500
5000
ms
Data Flash
300
T32Kpperase
32 KB block preprogram and erase time
Code Flash
—
300
600
5000
ms
Data Flash
400
T128Kpperase
128 KB block preprogram and erase time
Code Flash
—
600
1300
7500
ms
Data Flash
800
Teslat
D Erase Suspend Latency
—
30
s
TESRT
C Erase Suspend Request Rate
Code Flash
20
—
ms
Data Flash
10
—
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