參數(shù)資料
      型號(hào)： MPC5607BF0BCLU6
      廠商： FREESCALE SEMICONDUCTOR INC
      元件分類： 微控制器/微處理器
      英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176
      封裝： 24 X 24 MM, ROHS COMPLIANT, LQFP-176
      文件頁(yè)數(shù)： 95/110頁(yè)
      文件大?。?/td> 907K
      代理商： MPC5607BF0BCLU6
      Electrical
      charac
      teristics
      MPC5607B
      M
      icr
      ocontr
      oller
      Data
      Sheet,
      Re
      v
      .6
      Fre
      e
      scale
      Se
      mi
      condu
      cto
      r
      85
      4.18.2
      DSPI characteristics
      1 Operating conditions: T
      A = 25 °C, fperiph = 8 MHz to 64 MHz
      2 f
      periph is an absolute value.
      3 During the conversion, the total current consumption is given from the sum of the static and dynamic consumption,
      i.e., (41 + 46) * fperiph.
      Table 47. DSPI characteristics1
      No.
      Symbol
      C
      Parameter
      DSPI0/DSPI1/DSPI5/DSPI6
      DSPI2/DSPI4
      Unit
      Min
      Typ
      Max
      Min
      Typ
      Max
      1tSCK
      SR D SCK cycle time
      Master mode
      (MTFE = 0)
      125
      —
      333
      —
      ns
      DSlave mode
      (MTFE = 0)
      125
      —
      333
      —
      D
      Master mode
      (MTFE = 1)
      83
      —
      125
      —
      DSlave mode
      (MTFE = 1)
      83
      —
      125
      —
      —fDSPI
      SR D DSPI digital controller frequency
      —
      fCPU
      ——
      fCPU
      MHz
      —
      t
      CSC
      CC D Internal delay between pad
      associated to SCK and pad
      associated to CSn in
      master mode for CSn1->0
      Master mode
      —
      1302
      ——
      ns
      —
      t
      ASC
      CC D Internal delay between pad
      associated to SCK and pad
      associated to CSn in
      master mode for CSn1->1
      Master mode
      —
      1303
      —
      1303
      ns
      2tCSCext
      4
      SR D CS to SCK delay
      Slave mode
      32
      —
      32
      —
      ns
      3tASCext
      5
      SR D After SCK delay
      Slave mode
      1/fDSPI + 5
      —
      1/fDSPI + 5
      —
      ns
      4tSDC
      CC D SCK duty cycle
      Master mode
      —
      tSCK/2
      —
      tSCK/2
      —
      ns
      SR D
      Slave mode
      tSCK/2
      —
      tSCK/2
      —
      5tA
      SR D Slave access time
      Slave mode
      —
      1/fDSPI + 70
      —
      1/fDSPI + 130
      ns
      6tDI
      SR D Slave SOUT disable time
      Slave mode
      7
      —
      7
      —
      ns
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