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| 型號(hào)： | MPC5606SVLU6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件頁(yè)數(shù)： | 2/136頁(yè) |
| 文件大?。?/td> | 858K |
| 代理商： | MPC5606SVLU6 |
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
10
load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a
load-to-use dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined by the
Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as
move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and
branching.
Vectored and autovectored interrupts are supported. Hardware vectored interrupt support is provided to allow multiple interrupt
sources to have unique interrupt handlers invoked with no software overhead.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the Power Architecture
instruction set to be represented by a modified instruction set made up from a mixture of 16-bit and 32-bit instructions. This
results in a significantly smaller code size footprint without affecting performance noticeably.
The CPU core is enhanced by an additional interrupt source—Non Maskable Interrupt. This interrupt source is routed directly
from package pins, via edge detection logic in the SIU to the CPU, bypassing the Interrupt Controller completely. Once the edge
detection logic is programmed, it can not be disabled, except by reset. The Non Maskable Interrupt is, as the name suggests,
completely un-maskable and when asserted will always result in the immediate execution of the respective interrupt service
routine. The Non maskable interrupt is not guaranteed to be recoverable.
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When
Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt
source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
Additional features include:
Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
Thirty-two 32-bit general purpose registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Reservation instructions for implementing read-modify-write constructs
Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class instructions, can be interrupted
to prevent increases in interrupt latency
Extensive system development support through Nexus debug port
1.6.3
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port but one of those transfers must
be an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration
logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access
to a slave port in round-robin fashion, based upon the ID of the last master to be granted access.
The crossbar provides the following features:
4 master ports:
— e200z0h core instruction port
— e200z0h core complex load/store data port
— eDMA controller
— Display control unit
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