參數(shù)資料
型號(hào): MPC5606SVLQ6R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁(yè)數(shù): 21/136頁(yè)
文件大?。?/td> 858K
代理商: MPC5606SVLQ6R
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
117
3.20.8
I2C timing
Table 63. I2C Input Timing Specifications — SCL and SDA
No. Symbol C
Parameter
Value
Unit
Min
Max
1
CC
D Start condition hold time
2
IP-Bus Cycle1
1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
2
CC
D Clock low time
8
IP-Bus Cycle1
4
CC
D Data hold time
0.0
ns
6
CC
D Clock high time
4
IP-Bus Cycle1
7
CC
D Data setup time
0.0
ns
8
CC
D Start condition setup time (for repeated start condition only)
2
IP-Bus Cycle1
9
CC
D Stop condition setup time
2
IP-Bus Cycle1
Table 64. I2C Output Timing Specifications — SCL and SDA
No. Symbol C
Parameter
Value
Unit
Min
Max
11
1 Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
CC
D Start condition hold time
6
IP-Bus Cycle2
2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
CC
D Clock low time
10
IP-Bus Cycle1
33
3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
CC
D SCL/SDA rise time
99.6
ns
CC
D Data hold time
7
IP-Bus Cycle1
CC
D SCL/SDA fall time
99.5
ns
CC
D Clock high time
10
IP-Bus Cycle1
CC
D Data setup time
2
IP-Bus Cycle1
CC
D Start condition setup time (for repeated start condition only)
20
IP-Bus Cycle1
CC
D Stop condition setup time
10
IP-Bus Cycle1
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