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參數資料
| 型號： | MPC5534EVBISYS |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 15/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL ISYSTEMS MPC5534 |
| 標準包裝： | 1 |
| 類型： | 微控制器 |
| 適用于相關產品： | MPC5534 |
| 所含物品： | 評估板和演示軟件 |
| 相關產品： | MPC5554MZP132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MZP132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554AZP132-ND - IC MPU 2M FLASH 132MHZ 416-PBGA |
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MPC5534 Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
22
3.10
eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
1
ADC clock (ADCLK) frequency 1
1 Conversion characteristics vary with F
ADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a
maximum 16 factor.
FADCLK
112
MHz
2
Conversion cycles
Differential
Single ended
CC
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
ADCLK
cycles
3
Stop mode recovery time 2
2 Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform
conversions.
TSR
10
—
s
4
Resolution 3
3 At V
RH – VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.
—1.25
—
mV
5
INL: 6 MHz ADC clock
INL6
–4
4
Counts 3
6
INL: 12 MHz ADC clock
INL12
–8
8
Counts
7
DNL: 6 MHz ADC clock
DNL6
–3 4
4 Guaranteed 10-bit mono tonicity.
3 4
Counts
8
DNL: 12 MHz ADC clock
DNL12
–6 4
6 4
Counts
9
Offset error with calibration
OFFWC
–4 5
5 The absolute value of the offset error without calibration
100 counts.
4 5
Counts
10
Full-scale gain error with calibration
GAINWC
–8 6
6 The absolute value of the full scale gain error without calibration
120 counts.
8 6
Counts
11
Disruptive input injection current 7, 8, 9, 10
7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than
VRH, and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not
affect device reliability or cause permanent damage.
9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 This condition applies to two adjacent pads on the internal pad.
IINJ
–1
1
mA
12
Incremental error due to injection current. All channels are
10 k
< Rs <100 k
Channel under test has Rs = 10 k
,
IINJ = IINJMAX, IINJMIN
EINJ
–4
4
Counts
13
Total unadjusted error (TUE) for single ended conversions
with calibration 11, 12, 13, 14, 15
11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12 TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).
15 Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can
affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
TUE
–4
4
Counts
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