參數資料
型號: MPC5534AZQ40
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontroller
中文描述: 微控制器
文件頁數: 38/50頁
文件大小: 1148K
代理商: MPC5534AZQ40
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
38
3.13.7
eMIOS (MTS) Timing
3.13.8
DSPI Timing
Table 25. MTS Timing
1
1
MTS timing specified at F
SYS
= 80MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
T
A
= TL to TH, and CL = 50pF with SRC = 0b11.
Num
Characteristic
Symbol
Min
Max
Unit
1
eMIOS (MTS) Input Pulse Width
t
MIPW
t
MOPW
4
t
CYC
t
CYC
2
eMIOS (MTS) Output Pulse Width
1
Table 26. DSPI Timing
1
Num
Characteristic
Symbol
40 MHz
66 MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
1
SCK Cycle TIme
2,3
PCS to SCK Delay
4
After SCK Delay
5
t
SCK
t
CSC
t
ASC
t
SDC
25ns
2.9ms
17.9ns
2.0ms
15.2ns
1.7ms
2
23
15
13
ns
3
22
14
12
ns
4
SCK Duty Cycle
t
SCK
/2
–2ns
t
SCK
/2
+ 2ns
ns
5
Slave Access Time
(SS active to SOUT driven)
t
A
25
25
25
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
t
DIS
25
25
25
ns
7
PCSx to PCSS time
t
PCSC
t
PASC
t
SUI
4
4
4
ns
8
PCSS to PCSx time
5
5
5
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
6
Master (MTFE = 1, CPHA = 1)
20
2
–4
20
20
2
3
20
20
2
6
20
ns
ns
ns
ns
10
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
6
Master (MTFE = 1, CPHA = 1)
t
HI
–4
7
21
–4
–4
7
14
–4
–4
7
12
–4
ns
ns
ns
ns
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