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Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
19
3.9
Oscillator & FMPLL Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications
(V
DDSYN
= 3.0V to 3.6 V, V
SS
= V
SSSYN
= 0 V, T
A
= T
L
to T
H
)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
1
PLL Reference Frequency Range:
Crystal reference
External reference
Dual Controller (1:1 mode)
System Frequency
1
f
ref_crystal
f
ref_ext
f
ref_1:1
f
sys
t
CYC
f
LOR
f
SCM
8
8
24
20
20
f
sys
/2
f
MAX
2
1 / f
sys
1000
MHz
2
f
ico(min)
÷
2
RFD
—
MHz
3
System Clock Period
Loss of Reference Frequency
3
Self Clocked Mode (SCM) Frequency
4
ns
4
100
kHz
5
7.4
17.5
MHz
6
EXTAL Input High Voltage
Crystal Mode
5
All other modes (Dual Controller (1:1),
Bypass, External Reference)
V
IHEXT
V
IHEXT
Vxtal + 0.4v
((VDDE5/2) + 0.4v)
—
—
V
V
7
EXTAL Input Low Voltage
Crystal Mode
6
All other modes (Dual Controller (1:1),
Bypass, External Reference)
XTAL Current
7
V
ILEXT
V
ILEXT
—
—
Vxtal – 0.4v
((VDDE5/2) – 0.4v)
V
V
8
I
XTAL
C
S_XTAL
C
S_EXTAL
C
L
0.8
3
mA
9
Total On-chip stray capacitance on XTAL
—
1.5
pF
10
Total On-chip stray capacitance on EXTAL
—
1.5
pF
11
Crystal manufacturer’s recommended
capacitive load
See crystal
specification
See crystal
specification
pF
12
Discrete load capacitance to be connected
to EXTAL
C
L_EXTAL
—
2*C
L
– C
–
C
PCBS_EXTAL
2*C
L
– C
–
C
PCBS_XTAL
750
pF
13
Discrete load capacitance to be connected
to XTAL
PLL Lock Time
9
C
L_XTAL
—
pF
14
t
lpll
t
skew
—
μ
s
15
Dual Controller (1:1) Clock Skew (between
CLKOUT and EXTAL)
10, 11
Duty Cycle of reference
–2
2
ns
16
t
dc
f
UL
f
LCK
C
jitter
40
60
%
17
Frequency un-LOCK Range
– 4.0
4.0
% f
sys
% f
sys
18
Frequency LOCK Range
CLKOUT Period Jitter,
12, 13
Measured at f
SYS
Max
Peak-to-peak Jitter
(Clock edge to clock edge)
Long Term Jitter
(Averaged over 2 ms interval)
– 2.0
2.0
19
—
—
5.0
.01
% f
clkout