參數(shù)資料
型號(hào)： MPC5534AVZ40R2
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 39/50頁(yè)
文件大?。?/td> 1148K
代理商： MPC5534AVZ40R2
Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
39
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
11
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
t
SUO
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
ns
ns
ns
ns
12
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t
HO
–5
5.5
8
–5
—
—
—
—
–5
5.5
4
–5
—
—
—
—
–5
5.5
3
–5
—
—
—
—
ns
ns
ns
ns
1
DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, T
A
= TL to TH,
and CL = 50pF with SRC = 0b11.
2
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3
The actual minimum SCK Cycle Time is limited by pad performance.
4
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
5
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
6
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
Table 26. DSPI Timing
1
(continued)
Num
Characteristic
Symbol
40 MHz
66 MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
Data
Last Data
First Data
First Data
Data
Last Data
SIN
SOUT
PCSx
SCK Output
(CPOL=0)
4
9
12
1
11
10
4
SCK Output
(CPOL=1)
3
2
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