參數(shù)資料
型號: MPC5200VR400BR2
廠商: Freescale Semiconductor
文件頁數(shù): 19/72頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC52xx
核心處理器: e300
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器類型: 外部程序存儲器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
26
Freescale Semiconductor
NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst
on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 41 ×2×(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
Wait State is set to 10. => WS = 10
1+ 10 + 32 = 43 => CS is asserted for 43 PCI cycles.
3. ACK is output and indicates the burst.
4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
Figure 12. Timing Diagram—Burst Mode
t9
DATA hold after rising edge of PCI
clock
0
—ns
A7.32
t10
DATA hold after CS negation
0
(DC + 1) × tPCIck
ns
(4)
A7.33
t11
ACK assertion after CS assertion
—(WS + 1) × tPCIck
ns
A7.34
t12
ACK negation before CS negation
—7.0
ns
(3)
A7.35
t13
ACK pulse width
4LB ×2×(32/DS) ×tPCIck 4
LB ×2×(32/DS)×t
PCIck
ns
(2),(3)
A7.36
t14
CS assertion after TS assertion
—2.5
ns
A7.37
t15
TS pulse width
tPCIck
ns
A7.38
Table 25. Burst Mode Timing (continued)
Sym
Description
Min
Max
Units Notes SpecID
ADDR
DATA (rd)
CS[x]
R/W
OE
TS
t10
t3
t5
ACK
t1
PCI CLK
t2
t4
t7
t6
t11
t13
t14
t15
t9
t8
t12
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