參數(shù)資料
型號(hào)： MPC5200VR400B
廠商： Freescale Semiconductor
文件頁數(shù)： 6/72頁
文件大?。?/td> 0K
描述： IC MPU PROCESSOR 32BIT 272-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC52xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，J1850，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.42 V ~ 1.58 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 272-BBGA
包裝： 托盤
MPC5200B Data Sheet, Rev. 4
14
Freescale Semiconductor
1.3.4
Resets
The MPC5200B has three reset pins:
PORRESET—Power on Reset
HRESET—Hard Reset
SRESET—Software Reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Table 14
specifies the pulse widths of the Reset inputs.
For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards
its minimum pulse width equals the minimum given for HRESET related to the same reference clock.
The tVDD_stable describes the time which is needed to get all power supplies stable.
For tlock, refer to the Oscillator/PLL section of this specification for further details.
For tup_osc, refer to the Oscillator/PLL section of this specification for further details.
Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.
The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096
clock cycles.
NOTE
As long as VDD is not stable the HRESET output is not stable.
NOTE
Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter
to prevent them from getting into the chip. HRESET and SRESET must have a monotonous
rise time. The assertion of HRESET becomes active at Power on Reset without any
SYS_XTAL clock.
Table 14. Reset Pulse Width
Name
Description
Min Pulse Width
Max Pulse
Width
Reference Clock
SpecID
PORRESET
Power On Reset
tVDD_stable +tup_osc +tlock
—
SYS_XTAL_IN
A3.1
HRESET
Hardware Reset
4 clock cycles
—
SYS_XTAL_IN
A3.2
SRESET
Software Reset
4 clock cycles
—
SYS_XTAL_IN
A3.3
Table 15. Reset Rise/Fall Timing
Description
Min
Max
Unit
SpecID
PORRESET fall time
—
1
ms
A3.4
PORRESET rise time
—
1
ms
A3.5
HRESET fall time
—
1
ms
A3.6
HRESET rise time
—
1
ms
A3.7
SRESET fall time
—
1
ms
A3.8
SRESET rise time
—
1
ms
A3.9
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