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參數(shù)資料
| 型號： | MPC2105PDG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 64K X 64 CACHE TAG SRAM MODULE, 10 ns, DMA178 |
| 封裝： | DIMM-178 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 228K |
| 代理商： | MPC2105PDG66 |
MPC2104
MPC2105
MPC2106
MPC2107
19
MOTOROLA FAST SRAM
TAG RAM MATCH CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
Notes
Clock High Write to MATCH Invalid
tKHML
tKHMV
tAVMV
tAXMX
tGLML
tGHMX
—
7
ns
Clock High Read to MATCH Valid
—
10
ns
Address Valid to MATCH Valid
—
10
ns
MATCH Valid Hold from Address Change
2
—
ns
TOE Low to MATCH Invalid
—
7
ns
TOE High to MATCH Valid
—
8
ns
TAG RAM RESET (TCLR) CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
Notes
TCLR Set–up Time
tSTC
tHTC
tSRST
tSHRS
tRSML
tRSMV
tRSQZ
tRSQX
tPDSR
tRHWX
4
—
ns
TCLR Hold Time
1
—
ns
Status Bit Reset Time
—
60
ns
Status Bit Hold from TCLR Low
2
—
ns
TCLR Low to MATCH Invalid
—
10
ns
TCLR High to MATCH Valid
—
100
ns
TCLR Low to TAG High–Z
—
10
ns
TCLR High to TAG Active
—
100
ns
STANDBY Set–up to TCLR Low
30
—
ns
TCLR High to TWE Low
80
—
ns
AC TEST LOADS
OUTPUT
Z0 = 50
50
VL = 1.5 V
Figure 1A
Figure 1B
5 pF
+5 V
OUTPUT
255
480
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
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PDF描述 |
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| MPC2104 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2104SG66 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105ASG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105SG66 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105BSG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC2105SG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106ASG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106BSG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106CDG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106SG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
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