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參數(shù)資料
| 型號(hào)： | MPC184VFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SECURITY PROCESSOR 252-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 處理器類型： | MPC1xx PowerPC ISA PCI 橋/存儲(chǔ)器 |
| 速度： | 66MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 252-BGA |
| 供應(yīng)商設(shè)備封裝： | 252-MAPBGA（21x21） |
| 包裝： | 托盤 |
MOTOROLA
MPC184 Security Processor Technical Summary
5
Each data packet descriptor contains the following:
Header—The header describes the required services and encodes information that indicates which
EUs to use and which modes to set.
Seven data length/data pointer pairs—The data length indicates the number of contiguous bytes of
data to be transferred. The data pointer indicates the starting address of the data, key, or context in
system memory.
Next descriptor pointer
A data packet descriptor ends with a pointer to the next data packet descriptor. Therefore, once a descriptor
is processed and if the value of this pointer is non-zero, it is used to request a burst read of the next
descriptor.
Processing of the next descriptor (and whether or not a done signal is generated) is determined by the
programming of crypto-channel’s conguration register. Two modes of operation are supported:
Signal done at end of descriptor
Signal done at end of descriptor chain
The crypto-channel can signal done via an interrupt or by a write-back of the descriptor header after
processing a data packet descriptor. The value written back is identical to that of the header, with the
exception that a DONE eld is set.
Occasionally, a descriptor eld may not be applicable to the requested service. For example, if using DES
in ECB mode, the contents of the IV eld do not affect the result of the DES computation. Therefore, when
processing data packet descriptors, the crypto-channel skips any pointer that has an associated length of
zero.
6.1 External Bus Interface
The External Bus Interface (EBI) manages communication between the MPC184’s internal execution units
and the external bus. The interface is mode selectable between the 8xx bus protocols, used by the
PowerQuicc family of integrated communications processors, and the PCI 2.2 bus protocol. The MPC184
is unique in its ability to act as a bus master on the 8xx bus. All on-chip resources are memory mapped, and
the target accesses and initiator writes from the MPC184 must be addressed on word boundaries. The
MPC184 will perform initiator reads on byte boundaries and will adjust the data to place on word
boundaries as appropriate. The 8xx bus mastering interface allows the MPC184 to off-load both crypto
processing and data movement from the PowerQuicc processor, freeing the CPU for other networking
system functions, allowing the chipset to achieve best in class performance levels .
LEN_CTXOUT
PTR_CTXOUT
length
pointer
Length of output Context (IV)
Pointer to location where altered Context is to be written
nul length
nul pointer
length
pointer
Zeroes for xed length descriptor lter
nul length
nul pointer
length
pointer
Zeroes for xed length descriptor lter
PTR_NEXT
pointer
Pointer to next data packet descriptor
Table 6-1. Example Data Packet Descriptor
Field Name
Value/Type
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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