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參數(shù)資料
| 型號： | MN103SD0N |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 60 MHz, MICROCONTROLLER, PBGA257 |
| 封裝： | 11 X 11 MM, LEAD FREE, PLASTIC, UBGA-257 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 301K |
| 代理商： | MN103SD0N |
166
MAF00026AEM
MN103SD0 Series
Type
MN103SD0N
MN103SFD0R
Internal ROM type
Mask ROM
FLASH
ROM (byte)
768K
1024K
RAM (byte)
32K
40K
Package (Lead-free)
UBGA257-P-1111A (Under development)
Minimum Instruction
Execution Time
16.7 ns (at 1.65 V to 1.95 V, 60 MHz)
Interrupts
2C × 2, DMA × 18, WDT, A/D, System error
Timer Counter
8-bit timer × 8
Reload-down count, Cascade connection possible (usable as a 16-bit to 32-bit timer)
16-bit timer × 6
Up-down count, Input capture function, PWM generating function, Compare/capture register 2-ch.
16-bit timer × 6
Reload-down count
Watchdog timer × 1
Serial interface
Serial 0, 1, 3 to A : start-stop synchronization / synchronization commonly used, 10 lines
Serial 2 : start-stop synchronization / synchronization commonly used : 16 bytes containing transmission/reception FIFO
I2C : I2C serial interface, multi master transmission/reception function, 2 lines
DMA controller
Number of channels : 6
Unit of transfer : 8/16/32 bits
Max. Transfer cycles : 65535
Staring factor : external interrupt, timer factor, Input capture factor, PWM factor, serial transmission / reception factor, I2C transmission/
reception facto ｒ , A/D conversion finish, software factor
Transfer method : 2-bus cycle transfer
Adressing modes : fixed, increment, decrement
Transfer modes : word transfer, burst transfer, intermittent transfer
I/O Pins
I/O
194 : Common use
Input
1 : Exclusive
A/D converter
10-bit × 32-ch.
PWM
12-, 14-bit resolution × 6-ch.
ICR
28-bit × 13-ch. + 16-bit × 6-ch. (common with timer)
OCR
16-bit × 12-ch. (common with timer)
Timer Synchronous Output
4-bit (synchronous output) × 2-ch.
ROM Correction
8-ch.
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| MN103SD0Q | 32-BIT, MROM, 60 MHz, MICROCONTROLLER, PBGA257 |
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