
Electrical Specifications
QADC Electrical Characteristics
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA
Electrical Specifications
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593
Table 22-8. QADC Conversion Specifications
(V
DDH
and V
DDA
= 5.0 Vdc
±
0.5 V, V
DD
= 2.7 to 3.6 V
,
V
SS
= V
SSA
= 0 Vdc,
V
RH
– V
RL
= 5 V ± 0.5 V, T
A
= T
L
to T
H
)
No.
Parameter
Symbol
f
QCLK
Min
Max
Unit
1
QADC clock (QCLK) frequency
(1)
0.5
2.1
MHz
2
Conversion cycles
CC
14
28
QCLK
cycles
3
Conversion time, f
QCLK
= 2.0 MHz
Minimum = CCW/IST =%00
Maximum = CCW/IST =%11
t
CONV
7.0
14.0
μ
s
4
Stop mode recovery time
t
SR
—
10
μ
s
5
Resolution
(2)
—
5
—
mV
6
Absolute (total unadjusted) error
(3), (4), (5)
f
QCLK
= 2.0 MHz
(2)
, two clock input sample time
AE
–2
2
Counts
7
Disruptive input injection current
(6), (7), (8)
I
INJ(9)
–1
1
mA
8
Current coupling ratio
(10)
PQA
PQB
K
—
—
8x10
–5
8x10
–5
m
9
Incremental error due to injection current
All channels have same 10 k
< R
S
<100 k
Channel under test has R
S
= 10 k
,
I
INJ
= I
INJMAX
, I
INJMIN
Source impedance at input
(11)
E
INJ
—
—
—
+1.0
+1.0
+1.0
Counts
Counts
Counts
10
R
S
—
100
k
11
Incremental capacitance during sampling
(12)
C
SAMP
—
5
pF
1. Conversion characteristics vary with f
QCLK
rate. Reduced conversion accuracy occurs at max f
QCLK
rate. Using the QADC
pins as GPIO functions during conversions may result in degraded results.
2. At V
RH
– V
RL
= 5.12 V, one count = 5 mV
3. Accuracy tested and guaranteed at V
RH
– V
RL
= 5.0 V ± 0.5 V
4. Absolute error includes 1/2 count (~2.5 mV) of inherent quantization error and circuit (differential, integral, and offset) error.
Specification assumes that adequate low-pass filtering is present on analog input pins — capacitive filter with 0.01
μ
F to
0.1
μ
F capacitor between analog input and analog ground, typical source isolation impedance of 10 k
.
5. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals may
affect the conversion accuracy of other channels
6. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater
than V
RH
and $000 for values less than V
RL
. This assumes that V
RH
< V
DDA
and V
RL
> V
SSA
due to the presence of the
sample amplifier. Other channels are not affected by non-disruptive conditions.
7. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit
do not affect device reliability or cause permanent damage.
8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using V
POSCLAMP
= V
DDA
+ 0.5 V and V
NEGCLAMP
= – 0.3 V, then use the larger of the calculated values.
9. Condition applies to two adjacent pins.
10. Current coupling ratio, K, is defined as the ratio of the output current, I
Out
, measured on the pin under test to the injection
current, I
INJ
, when both adjacent pins are overstressed with the specified injection current. K = I
Out
/ I
INJ
The input voltage
error on the channel under test is calculated as V
ERR
= I
INJ
x K x R
S
.
— Continued —
F
Freescale Semiconductor, Inc.
n
.