OPERATIONAL MODES HALF-BRIDGE OUTPUT REGIS" />
參數(shù)資料
型號: MM908E621ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 31/60頁
文件大小: 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HALF-BRIDGE OUTPUT REGISTER (HBOUT)
HBx_H, HBx_L — Half-bridge Output Switches
These read/write bits select the output of each half-bridge
output according to Table . Reset clears all HBx_H, HBx_L
bits.
Half-bridge PWM mode
The PWM mode is selected by setting both HBxL and
HBxH of one half-bridge to “1”. In this mode, the high side
MOSFET is controlled by the incoming PWM signal on the
PWM pin (see Figure 2, page 2).
If the incoming signal is high, the high side MOSFET is
switched on.
If the incoming signal is low, the high side MOSFET is
switched off.
With the current recirculation mode control bit CRM in the
Half-bridge Status and Control Register (HBSCTL), the
recirculation behavior in PWM mode can be controlled. If
CRM is set, the corresponding low side MOSFET is switched
on, if the PWM controlled high side MOSFET is off.
Half-bridge Current Recopy
Each low side MOSFET has an additional sense output to
allow a current recopy feature. These sense sources are
internally amplified and switched to the Analog Multiplexer.
The factor for the Current Sense amplification can be
selected via the CSA bit in the A0MUCTL register (see
CSA = “1”: low resolution selected
CSA = “0”: high resolution selected
Half-bridge Over-temperature Protection
The outputs are protected against over-temperature
conditions. Each power output comprises two different
temperature thresholds.
The first threshold is the high temperature interrupt (HTI).
If the temperature reaches this threshold, the HTIF bit in the
Interrupt Flag Register (IFR) is set, and an interrupt will be
initiated if the HTIE bit in the Interrupt Mask register is set. In
addition, this interrupt can be used to automatically turn off
the power stages. This shutdown can be enabled/disabled by
the HTIS0-1 Bits in the System Control Register (SYSCTL).
The high temperature interrupts flag (HTIF) is cleared (and
the outputs reenabled) by writing a “1” to the HTIF flag in the
Interrupt Flag Register (IFR) or by a reset. Clearing this flag
has no effect as long as a high temperature condition is
present.
If the HTI shutdown is disabled, a second threshold high
temperature reset (HTR) will be used to turn off all power
stages (HB (all Fet’s), HS, HVDD, H0) in order to protect the
device.
Half-Bridge Over-current Protection
The Half-bridges are protected against short to GND,
VSUP, and load shorts. The over-current protection is
implemented on each HB. If an over-current condition on the
high side MOSFET occurs, the high side MOSFET is
automatically switched off. An over-current condition on the
low side MOSFET will automatically turn off the low side
MOSFET. In both cases, the corresponding HBxOCF flag in
the Half-bridge Status and Control Register (HBSCTL) is set.
The over-current status flag is cleared (and the
corresponding half-bridge MOSFETs reenabled) by writing a
“1” to the HBxOCF in the Half-bridge Status and Control
Register (HBSCTL) or by a reset.
Half-bridge Over-voltage/Under-voltage Protection
The half-bridge outputs are protected against under-
voltage and over-voltage conditions. This protection is done
by the low and high voltage interrupt circuitry. If one of these
flags (LVIF, HVIF) are set, the outputs are automatically
disabled when the VIS bit in the System Control Register
(SYSCTL) is cleared.
The over-voltage and under-voltage status flags are
cleared (and the outputs reenabled) by writing a “1” to the
LVIF / HVIF flags in the Interrupt Flag Register (IFR), or by a
reset. Clearing this flag has no effect as long as the high
voltage or low voltage condition is still present.
Register Name and Address: HBOUT - $01
Bit7
6
5
4
3
2
1
Bit0
Read
HB4_
H
HB4_
L
HB3_
H
HB3_
L
HB2_
H
HB2_
L
HB1_
H
HB1_
L
Write
Reset
0
Table 8. Half-bridge Configuration
HBx_H
HBx_L
Mode
0
Low side and high side MOSFET off
0
1
High side MOSFET off,
low side MOSFET on
1
0
High side MOSFET on,
low side MOSFET off
1
High side MOSFET in PWM mode
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