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參數(shù)資料
| 型號(hào)： | MM74HC4017 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Decade Counter/Divider with 10 Decoded Outputs |
| 中文描述： | 十年計(jì)數(shù)器/ 10解碼輸出分頻器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 126K |
| 代理商： | MM74HC4017 |
TL/F/5351
M
January 1988
MM54HC4017/MM74HC4017
Decade Counter/Divider with 10 Decoded Outputs
General Description
The MM54HC4017/MM74HC4017 is a 5-stage Johnson
counter with 10 decoded outputs that utilizes advanced sili-
con-gate CMOS technology. Each of the decoded outputs is
normally low and sequentially goes high on the low to high
transition of the clock input. Each output stays high for one
clock period of the 10 clock period cycle. The CARRY out-
put transitions low to high after OUTPUT 9 goes low, and
can be used in conjunction with the CLOCK ENABLE to
cascade several stages. The CLOCK ENABLE input dis-
ables counting when in the high state. A RESET input is
also provided which when taken high sets all the decoded
outputs low except output 0.
The MM54HC4017/MM74HC4017 is functionally and pinout
equivalent to the CD4017BM/CD4017BC. It can drive
up to 10 low power Schottky equivalent loads. All inputs are
protected from damage due to static discharge by diodes
from V
CC
and ground.
Features
Y
Wide power supply range: 2–6V
Y
Typical operating frequency: 30 MHz
Y
Fanout of 10 LS-TTL loads
Y
Low quiescent current: 80
m
A (74HC Series)
Y
Low input current: 1.0
m
A
Connection Diagram
Dual-In-Line and Flat Package
TL/F/5351–1
Order Number MM54HC4017 or MM74HC4017
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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相關(guān)代理商/技術(shù)參數(shù) |
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