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參數(shù)資料
| 型號： | MM74C195N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Registers |
| 中文描述： | CMOS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 127K |
| 代理商： | MM74C195N |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clock to Q or Q
V
CC
e
5V
V
CC
e
10V
150
75
300
130
ns
ns
t
pd
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clear to Q or Q
V
CC
e
5V
V
CC
e
10V
150
50
300
130
ns
ns
t
S
Time Prior to Clock Pulse that Data
must be Present
V
CC
e
5V
V
CC
e
10V
80
35
200
70
ns
ns
t
S
Time Prior to Clock Pulse that Shift/Load
must be Present
V
CC
e
5V
V
CC
e
10V
110
60
150
90
ns
ns
t
H
Time After Clock Pulse that Data
must be Held
V
CC
e
5V
V
CC
e
10V
b
10
b
5.0
0
0
ns
ns
t
W
Minimum Clear Pulse Width (t
WL
e
t
WH
)
V
CC
e
5V
V
CC
e
10V
100
50
200
100
ns
ns
t
W
Minimum Clear Pulse Width
V
CC
e
5V
V
CC
e
10V
90
40
130
60
ns
ns
t
r
, t
f
Maximum Clock Rise and Fall Time
V
CC
e
5V
V
CC
e
10V
5.0
2.0
m
s
m
s
f
MAX
Maximum Input Clock Frequency
V
CC
e
5V
V
CC
e
10V
2.0
5.5
3.0
8.5
MHz
MHz
C
IN
Input Capacitance
(Note 2)
5.0
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
(Note 3)
100
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
Capacitance is guaranteed by periodic testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
Truth Table
Inputs AT t
n
Outputs AT t
n
a
1
J
K
Q
A
Q
B
Q
C
Q
D
Q
D
L
L
H
H
H
L
H
L
Q
An
L
H
Q
An
Q
An
Q
An
Q
An
Q
An
Q
Bn
Q
Bn
Q
Bn
Q
Bn
Q
Cn
Q
Cn
Q
Cn
Q
Cn
Q
Cn
Q
Cn
Q
Cn
Q
Cn
Note:
H
e
High Level, L
e
Low Level
t
n
e
bit time before clock pulse
t
n
a
1
e
bit time after clock pulse
Q
An
e
State of Q
A
at t
n
Guaranteed Noise Margin
as a Function of V
CC
TL/F/5902–3
3
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