
Functional Description
(Continued)
Day of Week Counter
The day of week counter increments as the time rolls from
23:59 to 00:00 (11:59 PM to 12:00 AM in 12-hour mode). It
counts from 1 to 7 and rolls back to 1. Any day of the week
may be specified as day 1.
Clock Setting Register/Interrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the processor
at address 15. Normal clock and interrupt timing operations
will always continue regardless of which register is selected
onto the bus. The layout of these registers is shown in
Table II.
The clock setting register is comprised of three separate
functions:
a) leap year counter: bits 2 and 3
b) AM/PM indicator: bit 1
c) 12-hour mode set: bit 0 (see Table IIA).
The leap year counter is a 2-stage binary counter which
is clocked by the months counter. It changes state as the
time rolls over from 11:59 on December 31 to 00:00 on
January 1.
The counter should be loaded with the ‘number of years
since last leap year’ e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap year,
then the leap year counter should be set to 0. The contents
of the leap year counter can be read by the
m
P.
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from 11:59
to 12:00 in 12-hour mode. In 24-hour mode this bit is set to
logic 0.
The 12/24-hour mode set determines whether the hours
counter counts from 1 to 12 or from 0 to 23. It also controls
the AM/PM indicator, enabling it for 12-hour mode and forc-
ing it to logic 0 for the 24-hour mode. The 12/24-hour mode
bit is set to logic 0 for 12-hour mode and it is set to logic 1
for 24-hour mode.
IMPORTANT NOTE:
Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on Ini-
tialization (Methods of Device Operation) for a suggested
setting routine.
All bits in the clock setting register may be read by the proc-
essor.
The interrupt register controls the operation of the timer for
interrupt output. The processor programs this register for
single or repeated interrupts at the selected time intervals.
The lower three bits of this register set the time delay period
that will occur between interrupts. The time delays that can
be programmed and the data words that select these are
outlined in Table IIB.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode, logic 1 sets
for repeated mode.
Using the interrupt is described in the Device Operation sec-
tion.
TABLE IIA. Clock Setting Register Layout
Function
Data Bits Used
Comments
Access
DB3
DB2
DB1
DB0
Leap Year Counter
AM/PM Indicator (12-Hour Mode)
X
X
0 Indicates a Leap Year
0
e
AM
1
e
PM
0 in 24-Hour Mode
0
e
12-Hour Mode
1
e
24-Hour Mode
R/W
R/W
X
12/24-Hour Select Bit
X
R/W
TABLE IIB. Interrupt Control Register
Function
Comments
Control Word
DB3
DB2
DB1
DB0
No Interrupt
Interrupt output cleared,
start/stop bit set to 1.
X
0
0
0
0.1 Second
0.5 Second
1 Second
5 Seconds
10 Seconds
30 Seconds
60 Seconds
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
DB3
e
0 for single interrupt
DB3
e
1 for repeated interrupt
Timing Accuracy: single interrupt mode (all time delays):
g
1 ms
Repeated Mode:
g
1 ms on initial timeout, thereafter synchronous
with first interrupt (i.e., timing errors do not accumulate).
7