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參數(shù)資料
| 型號(hào)： | MM58167BN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Microprocessor Real Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | MM58167BN |
Functional Description
(Continued)
TABLE II. Clock RAM Bit Map for Alarm Interrupt Everyday at 10:15 a.m.
Address
Data
Function
Hi Nibble
Lo Nibble
4
3
2
1
0
7
6
5
4
3
2
1
0
Milliseconds
0
1
0
0
0
0
0
0
0
No RAM Exists
Hundredths and
Tenths of Seconds
0
1
0
0
1
0
0
0
0
0
0
0
0
Seconds
0
1
0
1
0
0
0
0
0
0
0
0
0
Minutes
0
1
0
1
1
0
0
0
1
0
1
0
1
Hours
0
1
1
0
0
0
0
0
1
0
0
0
0
Day of Week
0
1
1
0
1
No RAM Exists
1
1
X
X
Day of Month
0
1
1
1
0
1
1
X
X
1
1
X
X
Months
0
1
1
1
1
1
1
X
X
1
1
X
X
TABLE III. Address Codes and Function
A4
A3
A2
A1
A0
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CounterDMilliseconds
CounterDHundredths and Tenths of Seconds
CounterDSeconds
CounterDMinutes
CounterDHours
CounterDDay of Week
CounterDDay of Month
CounterDMonth
RAMDMilliseconds
RAMDHundredths and Tenths of Seconds
RAMDSeconds
RAMDMinutes
RAMDHours
RAMDDay of Week
RAMDDay of Month
RAMDMonths
Interrupt Status Register
Interrupt Control Register
Counters Reset
RAM Reset
Status Bit
GO Comand
STANDBY INTERRUPT
Test Mode
All others unused
The comparator is a cascaded exclusive NOR. Its output is
latched 61
m
s after the rising edge of the 1 kHz clock signal
(input to the milliseconds counter). This allows the counter
to ripple through before looking at the comparator. For oper-
ation at less than 4.5V, the thousandths of seconds counter
should not be included in a compare because of the possi-
bility of having a ripple delay greater than 61
m
s. (For output
timing see Interrupt Timing.)
Power Down Mode
The POWER DOWN input is essentially a second chip se-
lect. It disables all inputs and outputs except for the
STANDBY INTERRUPT. When this input is at a logical zero,
the device will not respond to any external signals. It will,
however, maintain timekeeping and turn on the STANDBY
INTERRUPT if programmed to do so. (The programming
must be done before the POWER DOWN input goes to a
4
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