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參數(shù)資料
| 型號： | MM1327 |
| 廠商： | MITSUMI ELECTRIC CO LTD |
| 元件分類： | 接收器 |
| 英文描述： | Wide Discriminator Monolithic IC |
| 中文描述： | VIDEO DISCRIMINATOR, PDIP30 |
| 封裝： | SDIP-30 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MM1327 |
MITSUMI
Wide Discriminator MM1327
Timing Chart 2
50IRE
0IRE
50IRE
100IRE
Y input
I (Q) input
MAX output
tegrated output
S/H
GP
HD
ADCLX
DATA
PEAK 05
00
+0.15V
-
0.15
3FM
00M
1. The largest of Y, I and Q video input signals is output on MAX output pin.
2. MAX output date is integrated during horizontal scanning.
3. Integration results are sampled and held at HD pulse timing.
4. Consecutive comparison ADC outputs data as serial data.
(Serial data is 1H delayed from video signal input.)
5. Output data configuration is as shown in the table below.
Data configuration
Video
DATA
White scanning
00
Black scanning
3F
Y input
PEAK
Peak of more than 50IRE
1
No peak of more than 50IRE
0
Timing Chart 3
1
0
1
1
0
DELAY
Y
IN
(22H)
NRZCLK
Integrated NRZCLK
(Internal circuit)
NRZ discrimination timing
1. When Y
IN
input signal matches "10110" at NRZ discrimination timing, it is identified as an EDTV2 signal.
EDTV2 pin is high for EDTV2 identification.
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