參數(shù)資料
型號(hào)： MM1313
廠商： MITSUMI ELECTRIC
英文描述： I2C BUS Control 5-Input 2-Output AV Switch
中文描述： I2C總線控制5聲道，2輸出AV系列開(kāi)關(guān)
文件頁(yè)數(shù)： 6/12頁(yè)
文件大?。?/td> 312K
代理商： MM1313
MITSUMI
I
2
C BUS Control 5-Input 2-Output AV Switch MM1313
Item
Symbol
Measure
Conditions (unless otherwise indicated,
Min. Typ. Max. Units
ment pin
Measurement Circuit Figure 1)
R
OUT
2 output
Voltage gain
G
R
2
F
R
2
THD
R
2
TP8
TP8
TP8
Sine wave 2.5V
P
-
P
, 1kHz
Sine wave 2.5V
P
-
P
, 1MHz/1kHz
-
3.0
Sine wave 2.5V
P
-
P
, 1kHz
Sine wave 1kHz
Maximum input for total higher
harmonic distortion factor < 0.5%
R
OUT
2 pin DC difference during
switching
-
0.5
0.0
0
0.03
0.5
1.0
0.1
dB
dB
%
Frequency characteristics
Total higher harmonic distortion
Input dynamic range
D
R
2
SG7
2.6
2.8
Vrms
Output offset voltage
V
OFFR
2
Z
OR
2
24
0
±15
mV
Output impedance
Crosswalk
V
OUT
1
V
OUT
2
Y
OUT
1
C
OUT
1
L
OUT
1
L
OUT
2
R
OUT
1
R
OUT
2
Video I/O Pin Voltage
Input pin voltage
120
C
TV
1
C
TV
2
C
TY
1
C
TC
1
C
TL
1
C
TL
2
C
TR
1
C
TR
2
TP1
TP2
TP3
TP6
TP4
TP5
TP7
TP8
Measurement Circuit Figure 2
for SG1 input : 4.43MHz, 1V
P
-
P
for SG2 input : 4.43MHz, 0.5V
P
-
P
-
60
-
60
-
60
-
60
-
90
-
90
-
90
-
90
-
53
-
53
-
53
-
53
-
80
-
80
-
80
-
80
dB
dB
dB
dB
dB
dB
dB
dB
Measurement Circuit Figure 2
1kHz, 2.5V
P
-
P
V
VIP
V
VOP
No signal, no load
V
OUT
1 pin, V
OUT
2 pin
No signal, no load
Y
OUT
1 pin, C
OUT
1 pin
No signal, no load
4.6
4.1
4.9
4.4
5.2
4.7
V
V
Output pin voltage
V
SOP
3.3
3.6
3.9
V
Audio I/O Pin Voltage
Input pin voltage
Output pin voltage
Logic section (Refer to figure below)
Input voltage L
Input voltage H
Low level output voltage (SDA)
High level input current
Low level input current
Clock frequency
Data transmission waiting time
SCL start hold time
SCL low level hold time
SCL high level hold time
SCL start set-up time
SDA data hold time
SDA data set-up time
SCL rise time
SCL fall time
SCL stop set-up time
V
AIP
V
AOP
No signal, no load
No signal, no load
4.0
3.9
4.3
4.2
4.6
4.5
V
V
V
IL
V
IH
V
OL
I
IH
I
IL
f
SCL
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SD;DAT
t
R
t
F
t
SU;STO
I
2
C logic low level discrimination value
I
2
Clogic high level discrimination value
SDA for 3mA inflow
when SDA, SCL=4.5V impressed
when SDA, SCL=0.4V impressed
0.0
3.0
0.0
-
10
-
10
1.5
5.0
0.4
+10
+10
100
V
V
V
μA
μA
kHz
μS
μS
μS
μS
μS
nS
nS
nS
nS
μS
4.7
4.0
4.7
4.0
4.7
200
250
1000
300
4.0
SDA
SCL
t
BUF
P
P
St
HD:STA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STD
t
LOW
Sr
t
R
t
F
I
2
C BUS BUS Control Signal
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