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參數(shù)資料
| 型號： | ML66Q517-NGA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 189K |
| 代理商： | ML66Q517-NGA |
FEDL66517-02
1Semiconductor
ML66517 Family
14/21
(2) External data memory control
(V
DD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
Cycle time
t
cyc
f
OSC = 25 MHz
40
—
Clock pulse width (HIGH level)
tφWH
13
—
Clock pulse width (LOW level)
tφWL
13
—
ALE pulse width
t
AW
2t
φ – 10
—
RD pulse width
t
RW
2t
φ – 18
—
WR pulse width
t
WW
2t
φ – 18
—
RD pulse delay time
t
RAD
t
φ – 5
—
WR pulse delay time
t
WAD
t
φ – 5
—
Low address setup time
t
ALS
2t
φ – 15
—
Low address hold time
t
ALH
t
φ – 13
—
High address setup time
t
AHS
3t
φ – 30
—
High address hold time
t
AHH
t
φ – 3
—
Read data setup time
t
RS
30
—
Read data hold time
t
RH
0t
φ – 3
Write data setup time
t
WS
2t
φ – 30
—
Write data hold time
t
WH
C
L = 50 pF
t
φ – 3
—
ns
Note: t
φ = t
cyc/2
tcyc
tφWH
tφWL
tAW
tRAD
tRW
tALS
CPUCLK
ALE
RD
AD0 to AD7
A8 to A15
tRS
tAHS
tRH
tAHH
Bus timing during no wait cycle time
tWAD
tWW
tALS
tALH
WR
AD0 to AD7
A8 to A15
tWS
tAHS
tWH
tAHH
RAP0 to 7
RAP8 to 15
DIN0 to 7
RAP0 to 7
DOUT0 to 7
RAP8 to 15
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