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FEDL64P168-01
Semiconductor
ML64P168
44/51
Capture circuit ( CAPR )
The ML64P168 captures 32Hz to 256Hz output of the time base counter at the falling of Port 0.0 or
Port 0.1 ( P0.0 or P0.1 ) to “L” level when the pull-up resistor input is chosen, or at the rising to “H”
level when the pull-down resistor input is chosen. The capture circuit is composed of the Capture
Control Register ( CAPCON ) and the Capture Registers ( CAPR0, CAPR1 ) that fetch output from
the time base counter.
Watchdog timer ( WDT )
The ML64P168 has a built-in watchdog timer to detect CPU malfunction. The watchdog timer is
composed of a 6-bit watchdog timer counter ( WDTC ) to count a 16Hz output and a watchdog
timer control register ( WDTCON ) to reset WDTC.
Clock generation circuit ( 2CLK )
The clock generation circuit ( 2CLK ) in the ML64P168 contains a 32.768kHz crystal oscillation
circuit, a 700kHz RC oscillation circuit, and a clock control port. This circuit generates the system
clock ( CLK ) and the time base clock ( 32.768kHz ).
The system clock drives the CPU while the time base clock drives the time base counter and the
buzzer driver.
Via the contents of the Frequency Control Register ( FCON ), the system clock can be switched
between 32.768kHz ( the output of the crystal oscillation circuit ) and 700kHz ( the output of the RC
oscillation circuit ).
Note: The oscillation frequency of the RC oscillation circuit varies depending on the value of an
external resistor ( ROS ), operating power supply voltage ( VDD ), and ambient temperatures
(Ta).
Time base counter ( TBC )
The ML64P168 has a built-in time base counter ( TBC ) that generates clocks to be supplied to
internal peripheral circuit. The time base counter is composed of 15 binary counters, and a 1/10
frequency dividing circuit. The count clock of the time base is driven by the oscillation clock
( 32.768kHz ) of the crystal oscillation circuit. The output of the time base counter is used for the
buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, the sampling
clocks of each port, and the capture circuit.
I/O port
Input-output ports ( P2, P3, P4 )
: 3 ports
× 4bits
Pull-up ( pull-down ) resistor input or high-impedance input, CMOS output or NMOS open
drain output: these can be specified for each bit; external 0 interrupt
Input port ( P0 )
: 1 port
× 4bits
Pull-up ( pull-down ) resistor input or high-impedance input; external 1 interrupt
Output port ( P1 )
: 1 port
× 4bits
CMOS output or NMOS open drain output