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參數(shù)資料
| 型號(hào)： | ML2037CP |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | DSP-NUM CONTROLLED OSCILLATOR, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 213K |
| 代理商： | ML2037CP |
ML2037
2
REV. 1.0 10/10/2000
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NAME
FUNCTION
1, 5
D GND
Ground connection for the digital
sections of the IC.
2
SYNC
Synchronization input. Holding this
pin low stops the sine wave output,
and resets the phase to zero.
3
CLK OUT
Output of the internal high frequency
clock generator. fCLK OUT = fCLK IN.
4
S CLK
Serial data clock input. Serial data is
clocked into the shift register on
falling edges of S CLK.
6
S DATA IN
Serial data input for programming the
output frequency.
7
S ENABLE
Serial interface enable control. A
logic high on this pin allows data to be
entered into the latch.
8
SHDN
A logic high on this pin causes the
output of the generator to shut off and
places the IC in a low power standby
mode.
PIN
NAME
FUNCTION
9
A GND
Ground reference for analog sections
of the IC and reference for OUT.
10
OUT
Sine wave output. The amplitude of
the sine wave will vary around a 2.5V
DC level.
11,12 AVCC
Power supply for the analog sections of
the IC.
13
CLK IN
Input of the internal high frequency
clock generator. This pin is either
driven from an external clock input or
connected to a crystal for use with the
internal oscillator.
14
G0
Output gain control. Works with G1 to
set the output amplitude to one of four
different full scale ranges.
15
G1
Output gain control. Works with G0 to
set the output amplitude to one of four
different full scale ranges.
16
DVCC
Power supply for the digital sections of
the IC.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D GND
SYNC
CLK OUT
S CLK
D GND
S DATA IN
S ENABLE
SHDN
DVCC
G1
G0
CLK IN
AVCC
OUT
A GND
TOP VIEW
ML2037
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
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