參數(shù)資料
型號(hào): MK5818SLFTR
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 16 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁(yè)數(shù): 3/7頁(yè)
文件大?。?/td> 138K
代理商: MK5818SLFTR
Spread Spectrum Clock Generator
MDS 5818 A
3
Revision 032206
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK5818
PRELIMINARY INFORMATION
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND, as close to these pins as
possible. For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used
trace impedance) place a 33
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI the 33W series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the MK5818. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. So,
for a crystal with a 16pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Spread Spectrum Profile
The MK5818 low EMI clock generator uses an
optimized frequency slew rate algorithm to facilitate
down stream tracking of zero delay buffers and other
PLL devices. The frequency modulation amplitude is
constant with variations of the input frequency.
Modulation Rate
The time required to transition from fMIN (minimum
frequency of the clock) to fMAX (maximum frequency of
the clock) and back to fMIN is the period of the
modualtion rate, TMOD. The modualtion rates of spread
spectrum clock generators are generally referred to in
terms of frequency, and fMOD = 1/TMOD .
The input clock frequency (fIN) and the internal divider
determine the modualtion rate.
The spread spectrum modulation rate (fMOD) is given
by the formula fMOD = fIN/DR, where:
fMOD is the modualtion rate, fIN is the input frequency,
and DR is the divider ratio (see table below).
Input Frequency Range
Divider Ratio (DR)
8 to 16 MHz
256
Ti m e
F
requen
c
y
Modulation Rate
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