參數(shù)資料
型號(hào): MK50N512CMC100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝: 8 X 8 MM, MAPBGA-121
文件頁數(shù): 26/69頁
文件大?。?/td> 1770K
代理商: MK50N512CMC100
Table 21. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
tnvmretp100 Data retention after up to 100 cycles
15
TBD
years
nnvmcycp
Cycling endurance
10 K
TBD
cycles
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
12
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
ns
EP9
EZP_CS negation to EZP_Q tri-state
12
ns
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
32
Preliminary
Freescale Semiconductor, Inc.
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