參數(shù)資料
型號: MK3727D
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/7頁
文件大?。?/td> 0K
描述: IC VCXO/PLL 24-36MHZ 8-SOIC
標(biāo)準(zhǔn)包裝: 97
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 36MHz
除法器/乘法器: 無/是
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
MK3727D
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO
VCXO AND SYNTHESIZER
IDT / ICS LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO
3
MK3727D
REV M 030806
External Component Selection
The MK3727D requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK, pin 5)
and the load is over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly used
trace impedance), place a 33
resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
Quartz Crystal
The MK3727D VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3727D incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3727D is designed to have zero
frequency error when the total of on-chip + stray
capacitance is
14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3727D. There should be no vias between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
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