參數(shù)資料
型號: MK3723DTR
元件分類: 時鐘產(chǎn)生/分配
英文描述: 14 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 3/6頁
文件大?。?/td> 79K
代理商: MK3723DTR
LOW COST 3.3 VOLT VCXO
MDS 3723 C
3
Revision 070601
Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q
w w w. icst . c om
MK3723
External Component Selection
The MK3723 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01
F should be connected
between VDD and GND on pin 2 and 4, as close to the
MK3723 as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used
trace impedance) place a 33
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Quartz Crystal
The MK3723 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3723 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3723 is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°C±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3723. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3723 to 3.3V. Connect pin 3
of the MK3723 to the second power supply. Adjust the
voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
Error
10
6
x
f
3.0V
f
tet
arg
()
f
0V
f
tet
arg
()
+
f
tet
arg
------------------------------------------------------------------------------
error
xtal
=
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