參數(shù)資料
型號: MK3722GTR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 27 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: 4.40 MM, 0.65 MM PITCH, TSSOP-16
文件頁數(shù): 2/7頁
文件大?。?/td> 182K
代理商: MK3722GTR
MK3722
VCXO PLUS AUDIO CLOCK FOR STB
VCXO AND SYNTHESIZER
IDT / ICS VCXO PLUS AUDIO CLOCK FOR STB
2
MK3722
REV E 062206
Pin Assignment
Pin Descriptions
Audio Clock Select Table
12
1
11
2
10
3
9
X2
4
X1
5
VD D
6
NC
7
VD D
8
VIN
VD D
S0
27M
GN D
S2
GN D
AC LK
16
15
14
13
PD TS
S1
16 Pin 4.40m m body, 0.65m m pitch T SSO P
S2
S1
S0
ACLK (MHz)
00
0
8.192
0
1
11.2896
0
1
0
12.288
0
1
16.9344
1
0
18.432
1
0
1
16.384
1
0
22.5792
1
24.576
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Output
Crystal connection. Connect to a 27MHz fundamental mode
pullable crystal.
2
X1
Input
Crystal connection. Connect to a 27MHz fundamental mode
pullable crystal.
3
VDD
Power
Connect to +3.3 V.
4
VDD
Power
Connect to +3.3 V.
5
VIN
Input
Voltage input to VCXO. Zero to 3.3V signal which controls the
VCXO frequency.
6
GND
Power
Connect to ground.
7
GND
Power
Connect to ground.
8PDTS
Power
Power Down Tri-state. This pin powers down entire chip and
tri-states the outputs when low. Internal pull-up.
9
S2
Input
Select input S2. Selects ACLK per table above. Internal pull-up.
10
ACLK
Output
Audio clock output per table above.
11
GND
Power
Connect to ground.
12
27M
Output
27MHz reference clock output.
13
S0
Input
Select input S0. Selects ACLK per table above. Internal pull-up.
14
VDD
Power
Connect to +3.3V.
15
NC
--
No connect. Do not connect anything to this pin.
16
S1
Input
Select input S1. Selects ACLK per table above. Internal pull-up.
相關PDF資料
PDF描述
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