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參數(shù)資料
| 型號： | MK3713SLFTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 10 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 59K |
| 代理商： | MK3713SLFTR |
MK3713
Low Cost 3.3 Volt VCXO
MDS 3713 B
3
Revision 020900
Printed 11/16/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
I C R O
C LOC K
PRELIMINARY INFORMATION
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.15
3.30
3.45
V
Output High Voltage, VOH
IOH=-12mA
2.4
V
Output Low Voltage, VOL
IOL=12mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-4mA
VDD-0.4
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Operating Supply Current, IDD
No Load
7
mA
Short Circuit Current
±50
mA
VIN, VCXO control voltage
0
3.3
V
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Crystal Frequency
10
20
MHz
Input Crystal Accuracy
±30
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
50
60
%
Output Clock Pullability, note 2
0V
≤ VIN ≤ 3.3 V
±100
ppm
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With a ICS/MicroClock approved pullable crystal.
External Components
The MK3713 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01F should be connected between VDD and GND on pins 2 and 4, as close to the
MK3713 as possible. A series termination resistor of 33
may be used for the clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel mode,
pullable, AT cut, 13.5 MHz, with 14 pF load capacitance. Consult ICS for recommended suppliers.
IMPORTANT - read application note MAN05 before laying out the PCB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK3713STR | 10 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK3713SLFTR | 10 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK3720DLF | 54 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK3720D | 54 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK3722GTR | 27 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK3713STR | 制造商:ICS 制造商全稱:ICS 功能描述:Low Cost 3.3 Volt VCXO |
| MK3715 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW COST 3.3 VOLT VCXO |
| MK3715S | 制造商:ICS 制造商全稱:ICS 功能描述:LOW COST 3.3 VOLT VCXO |
| MK3715STR | 制造商:ICS 制造商全稱:ICS 功能描述:LOW COST 3.3 VOLT VCXO |
| MK3720 | 制造商:ICS 制造商全稱:ICS 功能描述:27 MHz and 54 MHz 3.3 Volt VCXO |
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