參數(shù)資料
型號: MK2744-08SLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 81 MHz, VIDEO CLOCK GENERATOR, PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 3/4頁
文件大?。?/td> 44K
代理商: MK2744-08SLF
MK2744
MPEG/Set-Top Clock Source
MDS2744D
3
Revision 9297
Printed 12/4/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.5
5.5
V
Input High Voltage, VIH, X1/ICLK pin only
3.5
2.5
V
Input Low Voltage, VIL, X1/ICLK pin only
2.5
1.5
V
Input High Voltage, VIH, AS1 pin
Pin 12 only
VDD-0.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
37
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
7
pF
Frequency error, ACLK and 3.6864MHz clocks
note 3
0
ppm
Frequency error, 24.576 MHz ACLK only
40
ppm
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
27.000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
60
%
Absolute Jitter, short term
Variation from mean
200
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With Processor clock at 50MHz, and ACLK at 16.93MHz.
3. The 24.576 MHz audio clock is not 0ppm accurate. It runs at 40ppm high.
External Components
The MK2744 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND, as close to the MK2744 as possible. A
series termination resistor of 33
may be used for each clock output. If a clock input is not used, the
27.00 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode (don’t use third overtone), parallel resonant, 50ppm or better. Crystal capacitors should be connected
from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation,
where CL is the crystal load capacitance: Crystal caps (pF) = (CL-4) x 2. So for a crystal with 16pF load
capacitance, two 24pF caps should be used.
相關(guān)PDF資料
PDF描述
MK2744-09SLFTR 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16
MK2745-20STR 108 MHz, VIDEO CLOCK GENERATOR, PDSO16
MK2745-20STRLF 108 MHz, VIDEO CLOCK GENERATOR, PDSO16
MK2745-24STRLF 60 MHz, VIDEO CLOCK GENERATOR, PDSO16
MK2745-24SLF 60 MHz, VIDEO CLOCK GENERATOR, PDSO16
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參數(shù)描述
MK2745-21 制造商:ICS 制造商全稱:ICS 功能描述:DVD/MPEG Clock Source
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MK2745-21SLF 功能描述:時鐘合成器/抖動清除器 DVD/MPEG CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
MK2745-21SLFTR 功能描述:時鐘合成器/抖動清除器 DVD/MPEG CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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