參數(shù)資料
型號(hào): MK2722-01SLFTR
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: 50 MHz, VIDEO CLOCK GENERATOR, PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁(yè)數(shù): 3/4頁(yè)
文件大小: 56K
代理商: MK2722-01SLFTR
MK2722
Sigma Designs Clock Source
MDS 2722 B
3
Revision 020802
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295 9800tel www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
4.5
5
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-4mA
VDD-0.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Operating Supply Current, IDD, 5.0V
No Load
30
mA
Power Down Supply Current, IDDPD, 5V
No Load, note 2
25
A
Short Circuit Current
Each output
±50
mA
Input Capacitance
7
pF
On chip pull-up resistor
Pins 6, 8, 12, 15, and 16
250
k
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency
27.000
MHz
Input Crystal Accuracy
±30
ppm
Frequency Error, all clocks
0
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
50
60
%
Maximum Absolute Jitter, short term
200
ps
Electrical Specifications
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With AS1=AS0=BS1=BS0=VDD
External Components
The MK2722 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1F should be connected between VDD and GND (pins 4 and 5, 13 and 11), as close to the MK2722 as possible.
A series termination resistor of 33
may be used for each clock output. If a clock input is not used, a 27 MHz
fundamental mode crystal must be connected as close to the chip as possible. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground. The value (in pF) of these crystal capacitors should be = (CL-
12)*2, where CL is the crystal load capacitance in pF. So for a crystal with 16pF load capacitance, the crystal
capacitors should be 8pF each.
相關(guān)PDF資料
PDF描述
MK2722-01SLF 50 MHz, VIDEO CLOCK GENERATOR, PDSO16
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MK2722-01SLF 50 MHz, VIDEO CLOCK GENERATOR, PDSO16
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