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參數(shù)資料
| 型號： | MK2475-24SLFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 60 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 119K |
| 代理商： | MK2475-24SLFT |
DVD/MPEG CLOCK SOURCE
MDS 2745-24 C
2
Revision 111903
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK2745-24
Pin Assignment
Processor Clock (in MHz)
Audio Clocks Selection Table (in MHz)
Pin Descriptions
1
2
3
GND
4
X2
5
6
27M
7
8
PCLK
VDD
PCS
ACS0
ACS1
27M
ACLK/256
X1/CLK
16
VDD
ACLK/8
ACLK
GND
15
14
13
12
11
10
9
16-pin (150 mil) SOIC
GND
PCS
PCLK
040
160
ACS1
ACS0
ACLK
ACLK/8
ACLK/256
0
24.576
3.072
96.0 kHz
0
1
11.2896
1.4112
44.1 kHz
1
0
8.192
1.024
32.0 kHz
1
12.288
1.536
48.0 kHz
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
GND
Power
Connect to ground.
2
X2
XO
Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock
input.
3
X1/CLK
X1
Crystal connection. Connect to 27 MHz crystal or connect to 27 MHz input
clock.
4
VDD
Power
Connect to +3.3 V or +5 V. Must be same as other VDD.
5
GND
Power
Connect to ground.
6
27M
Output
27.00 MHz clock output.
7
ACS0
Input
Audio Clock Select 0. Selects audio clocks per table above.
8
ACLK/8
Output
Audio Clock divided by 8 output. Determined by status of ACS1, ACS0. See
table above.
9
ACLK/256
Output
Audio Clock divided by 256 output. Determined by status of ACS1, ACS0. See
table above.
10
PCS
Input
Processor Clock Select pin. Selects PCLK per table above.
11
ACLK
Output
Audio Clock output. Determined by status of ACS1, ACS0. See table above.
12
GND
Power
Connect to ground.
13
VDD
Power
Connect to +3.3 V or +5 V. Must be same as other VDD.
14
PCLK
Output
Processor Clock output. Determined by status of PCS. See table above.
15
27M
Output
27.00 MHz clock output.
16
ACS1
Input
Audio Clock Select 1. Selects audio clocks per table above.
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