參數(shù)資料
型號(hào): MK2308S-2TR
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/6頁(yè)
文件大?。?/td> 0K
描述: IC PLL ZD BUFFER HS 16-SOIC
產(chǎn)品變化通告: Product Discontinuation 13/May/2009
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 零延遲緩沖器
PLL: 帶旁路
輸入: 時(shí)鐘
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 133.3MHz
除法器/乘法器: 是/是
電源電壓: 3 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
ZDB
IDT ZERO DELAY, LOW SKEW BUFFER
2
MK2308-2
REV E 051310
Pin Assignment
Feedback Configuration Table
Output Clock Mode Select Table
Pin Descriptions
1
2
3
GND
4
CLKA1
5
6
CLKA4
7
8
CLKA3
VDD
CLKB3
CLKB2
FBIN
CLKB1
S1
CLKA2
16
CLKIN
VDD
S2
CLKB4
GND
15
14
13
12
11
10
9
16-pin (150 mil) SOIC
Feedback From
CLKA1:A4
CLKB1:B4
Bank A
CLKIN
CLKIN/2
Bank B
2XCLKIN
CLKIN
S2
S1
Clocks A1:A4
Clocks B1:B4
Internet Generation
PLL Status
0
Tri-state (high impedance)
None
On
0
1
Running
Tri-state (high impedance)
PLL
On
1
0
Running
Buffer only (no zero delay)
Off
1
Running
PLL
On
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
CLKIN
Input
Clock input. Connect to input clock source.
2 - 3
CLKA1:A4
Output
Clock A bank of four outputs.
4
VDD
Power
Power supply. Connect pin to same voltage as pin 13 (either 3.3 V ).
5
GND
Power
Connect to ground.
6 - 7
CLKB1:B4
Output
Clock B bank of four outputs. These are low skew divide by two of bank A.
8
S2
Input
Select input 2. Selects mode for outputs per table above.
9
S1
Input
Select input 1. Selects mode for outputs per table above.
10 - 11
CLKB1:B4
Output
Clock B bank of four outputs. These are low skew divide by two of bank A.
12
GND
Power
Connect to ground.
13
VDD
Power
Power supply. Connect pin to same voltage as pin 4 (either 3.3 V ).
14 - 15
CLKA1:A4
Output
Clock A bank of four outputs.
16
FBIN
Input
Feedback input. Determines outputs per table above.
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