參數(shù)資料
型號(hào)： MK20DN512ZVMB10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
封裝： 8 X 8 MM, MAPBGA-81
文件頁數(shù)： 32/73頁
文件大小： 1046K
代理商： MK20DN512ZVMB10
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
—
50
MHz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
—
11.5
ns
FB3
Address, data, and control output hold
0.5
—
ns
FB4
Data and FB_TA input setup
8.5
—
ns
FB5
Data and FB_TA input hold
0.5
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.71
3.6
V
Frequency of operation
—
TBD
MHz
FB1
Clock period
TBD
—
ns
FB2
Address, data, and control output valid
—
13.5
ns
FB3
Address, data, and control output hold
0
—
ns
FB4
Data and FB_TA input setup
13.7
—
ns
FB5
Data and FB_TA input hold
0.5
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
38
Preliminary
Freescale Semiconductor, Inc.
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